Strained channel is promising for promoting MOSFET transistor performance by enhancing carrier mobility. Specifically, PMOS prefers compressive strain and NMOS prefers tensile strain. In a conventional planar process for making strained channel transistors, a strained layer is formed as the transistor channel prior to transistor gate dielectric formation. The property of the strained channel is however degraded by subsequent processing. For example, the high temperature gate oxidation process induces species diffusion and strain relaxation. Additionally, for a strained material different from silicon, a silicon cap on the top is typically required due to the general incompatibility of the strained layer and a gate dielectric. The silicon cap layer degrades the efficiency of the strained layer as the carrier conducting layer.
A conventional method of inducing a strained channel transistor after transistor gate stack formation is to etch the deep source/drain regions of a transistor and then embed a stressor material in the recessed areas where the deep source/drain regions were. This etch and refill method typically occurs after the formation of offset spacers. However, known methods that embed a stressor material in the deep source/drain generally fail to achieve a transistor having high strain with permissible defectivity control. The inadequacies are due to the amount of separation that exists from the stressor material to the channel region due in part to the presence of the offset spacers. However, if the stressor material is increased in size (i.e. depth) to enhance the amount of stress, the increased amount of stressor material functions to increase defectivity of the stressor material which reduces the amount of the stress the stressor material provides and increases the amount of transistor current leakage.
In another method, a stressor material is applied in the source/drain extension region after the formation of a gate electrode and a gate spacer. Afterwards, source/drain dopant implantation is performed and followed by an anneal. However, this implantation relaxes the deposited stressor material and thereby degrades the amount of strain that the stressor material applies on the channel. Further, the dopant profile of the source/drain extension and the source/drain is not abrupt due to the anneal.
In yet another method, the source/drain extension region of a transistor must be recessed and filled with insitu doped SiGe or SiC separately with deep source/drain recess in order to maintain the shallow extension for controlling the short channel effect.
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